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Clock Synchronizer/Adapter for Communications
September 2006
XRT8000
FEATURES D Clock Adaptation for Most Popular Telecommunication Frequencies D Wide Input Frequency Range D Programmable Output Frequencies D Less than 0.05UI Wide Band Output Jitter D Low Power Operation (5V and 3.3V) D Maximum Lock Time of 45mS GENERAL DESCRIPTION The XRT8000 is a dual phase-locked loop chip that generates two simultaneous, very low jitter, output clocks for synchronization applications in wide area networking systems. The outputs are phase locked to the input signal. The chip has four basic modes of operation; referred to as master (FORWARD, REVERSE) and slave (FORWARD, REVERSE) modes (See Figure 1). In the FORWARD mode it accepts up to 16th harmonic of either 1.544MHz or 2.048MHz as input reference and generates 1.2kHz and multiples of 2.4kHz, 56kHz or 64kHz. In the REVERSE mode an input clock of 56kHz or 64kHz is used ORDERING INFORMATION
Part No. XRT8000IP XRT8000ID Package 18 Lead 300 Mil PDIP 18 Lead 300 Mil JEDEC SOIC Operating Temperature Range -40C to +85C -40C to +85C
D Cascadable D No External Components Needed D Lock Detect Indication Pin APPLICATIONS D DSU's, CSU's and Access Equipment D ISDN Terminals D Concentrators and Multiplexers
to generate 1.544MHz or 2.048MHz output clocks. The SLAVE (FORWARD, REVERSE) modes generate the same output frequencies as the MASTER (FORWARD/ REVERSE MODES) except that the input frequency (FIN) is 8kHz. An optional divide by eight can be enabled at each of the outputs. The input and output frequency selection can be done through a serial microprocessor interface. The XRT8000 is available in either 18 pin SOIC package or 18 pin plastic DIP.
XRT8000 CLK2 n x 1.544{T1} n x 2.048{E1} 1 <= n <= 16 FIN CLK1 K x 56kHz K x 64kHz 1.2kHz 2.4 x K to 43.2kHz SYNC 8kHz 1 <= K <= 32 56kHz 64kHz
XRT8000 CLK2 FIN CLK1
XRT8000
B
T1 (1.544) or E1 (2.048) SYNC 8kHz
CLK2 FIN CLK1
A
1 <= K <= 18
A/ B
SYNC
MASTER FORWARD
MASTER REVERSE
SLAVE FORWARD/REVERSE
Figure 1. System Diagram
Rev.1.11
E1999--2006 EXAR Corporation, 48720 Kato Road, Fremont, CA 94538 z (510) 668-7000 z FAX (510) 668-7017 z www.exar.com
XRT8000
BLOCK DIAGRAM
Analog PhaseLocked Loop
Post Divider
Q
Div. By 8
Driver
CLK2
Feedback Divider M
Q2
DIV/8_EN PLL 2
M2
Lock Detector
LOCKDET SYNC
FIN VCC
Input Divider
P
Analog PhaseLocked Loop
Post Divider
Q
Div. By 8
Driver
CLK1
R 100K
R 100K
Feedback Divider M PLL 1 M2 Q2 DIV/8_EN
SCLK CSB SDI SDO MSB
Serial Interface
Mode and Frequency Select Control
Figure 2. Block Diagram
Rev. 1.11 2
XRT8000
PIN CONFIGURATION
SDO SYNC FIN GND GND CLK1 VCC MSB GND
1 2 3 4 5 6 7 8 9 18 17 16 15 14 13 12 11 10
SCLK CSB SDI VCC GND CLK2 VCC LOCKDET VCC
SDO SYNC FIN GND GND CLK1 VCC MSB GND
1 2 3 4 5 6 7 8 9
18 17 16 15 14 13 12 11 10
SCLK CSB SDI VCC GND CLK2 VCC LOCKDET VCC
18 Lead PDIP (0.300")
18 Lead SOIC (Jedec, 0.300")
PIN DESCRIPTION
Symbol SDO SYNC FIN GND GND CLK1 VCC MSB Pin# 1 2 3 4 5 6 7 8 I O Type O O I Description Serial Data Output (Microprocessor Serial Interface). Data output from the command registers. An 8kHz Signal SubDivided From FIN. This output can be threestated via CR5. SYNC can be used to synchronize other XRT8000 which are configured in slave modes. Reference Frequency Input. Digital Ground. Digital Ground. Clock 1. Output of the phase-locked loop 1. Digital Positive Power Supply. Master/Slave Mode Select Input. If this input is high, then the MASTER mode is selected. If this input is low, then the SLAVE mode is enabled. This pin is internally pulled up via 100KW resistor. Analog Ground. Analog Positive Supply. O Lock Detect. This output is high when both phase-locked loops are in lock and will go low if either one of the phase locked loops loses lock. Digital Positive Power Supply. O Clock 2. Output of the phase-locked loop 2. Digital Ground. Digital Positive Power Supply. I I I Serial Data Input (Microprocessor Serial Interface) Data input to the command registers. Chip Select Not (Microprocessor Serial Interface) . When this input is low the data in and out will be shifted in the appropriate registers. Internal pull up (100K). Serial Clock Input (Microprocessor Serial Interface) . This clock will serve as a reference to the data streams to SDI and SDO (the positive edge of SCLK is used to latch the data).
GND VCC LOCKDET VCC CLK2 GND VCC SDI CSB SCLK
9 10 11 12 13 14 15 16 17 18
Rev. 1.11 3
XRT8000
DC ELECTRICAL CHARACTERISTICS (Except Serial Interface) Operating Temperature: -40_C to 85_C Test Conditions: TA = 25_C, VCC = 5.0V 5% Unless Otherwise Specified
Symbol VIL VIH VOL VOH VOL VOH IIL IIH IIL IIH ICC RIN Parameter Input low level Input high level Output low level (CLK1,CLK2) Output high level (CLK1,CLK2) Output low level (LOCKDET,SYNC) Output high level (LOCKDET,SYNC) Input low current (CSB,MSB) Input high current (CSB,MSB) Input low current (except CSB,MSB) Input high current (except CSB,MSB) Operating current Input pull-up resistance (CSB,MSB) Min 2.0 0.4 2.4 0.4 2.4 -150 10 -10 20 100 10 35 150 Typ Max 0.8 Unit V V V V V V mA mA mA mA mA KW Conditions
IOL = -6.0 mA IOH = 6.0 mA IOL = -3.0 mA IOH = 3.0 mA VIN = VCC VIN = VCC No load. Clock = 2.1 MHz
50
AC ELECTRICAL CHARACTERISTICS (See Figure 3)
Symbol T1 T2 T3 T61 T74 T74 T74 T74 T74 T8 T9 T10 T112 Parameter Input frequency Minimum input signal high to low duration Output frequency Duty cycle CLK1, CLK2 Jitter added 8KHz-40KHz Jitter added 10Hz-40KHz Broad Band-jitter Jitter added 20Hz-100KHz Jitter added 18kHz-100KHz Capture time Clock output rise time Clock output fall time Duty cycle SYNC 40 Spec.3 Min 0.008 12 1.2 47.5 0.025 0.025 0.05 1.5 0.2 Typ Max 32.7 Unit MHz ns KHz % UI UI UI UI UI ms ns ns % Conditions
50 0.007 0.022 0.03 0.05 0.01
2.1 52.5 0.02 0.05 0.07 0.03 40 10 10 60
VCC/2 switch point. 30pF load. Output =1.544MHz Output =1.544MHz Output =1.544MHz Output =2.048MHz Output =2.048MHz 30pF load. Measured at 20/80 % 30pF load. Measured at 20/80 % VCC/2 switch point (in master forward mode). 30pF load. See table 12 for values of T
T14
Delay time between the rising edge of SYNC and the rising edge of CLK1 or CLK2
T-20
T
T+20
ns
Notes: T4
1
T 12
2
T6 = ( T4 + T5 )
T11 =
( T 12 + T 13 )
3 4
Specifications from AT&T Publication 62411 and ITU-T Recommendations G-823 (for 1.544MHz and 2.048MHz, respectively). T7 is guaranteed by characterization, not tested. Specifications are subject to change without notice. Rev. 1.11 4
XRT8000
DC ELECTRICAL CHARACTERISTICS (Except Serial Interface) Operating Temperature: -40_C to 85_C Test Conditions: TA = 25_C, VCC = 3.3V 5% Unless Otherwise Specified
Symbol VIL VIH VOL VOH VOL VOH IIL IIH IIL IIH ICC RIN Input low level Input high level Output low level (CLK1,CLK2) Output high level (CLK1,CLK2) Output low level (LOCKDET,SYNC) Output high level (LOCKDET,SYNC) Input low current (CSB,MSB) Input high current (CSB,MSB) Input low current (except CSB,MSB) Input high current (except CSB,MSB) Operating current Input pull-up resistance (CSB,MSB) 50 11 100 -10 10 30 150 2.4 -150 10 2.4 0.4 2.0 0.4 Parameter Min Typ Max 0.8 Unit V V V V V V mA mA mA mA mA KW VIN = VCC No load. Clock = 2.1 MHz VIN = VCC IOL = -3 mA IOH = 3 mA IOL = -2.5 mA IOH = 2.5 mA Conditions
AC ELECTRICAL CHARACTERISTICS (See Figure 3)
Symbol T1 T2 T3 T61 T74 T74 T74 T74 T74 T8 T9 T10 T112 Parameter Input frequency Minimum input signal high to low duration Output frequency Duty cycle CLK1, CLK2 Jitter added 8KHz-40KHz Jitter added 10Hz-40KHz Broad Band Jitter added 20Hz-100KHz Jitter added 18kHz-100KHz Capture time Clock output rise time Clock output fall time Duty cycle SYNC 40 0.025 0.025 0.05 1.5 0.2 Spec.3 Min 0.008 12 1.2 47.5 50 0.01 0.030 0.035 0.045 0.010 0.05 0.07 0.03 40 14 14 60 2.1 52.5 0.02 Typ Max 32.7 Unit MHz ns KHz % UI UI UI UI UI ms ns ns % 30pF load. Measured at 20/80 % 30pF load. Measured at 20/80 % VCC/2 switch point (in master forward mode). 30pF load. T14 Notes: T4
1 3 4
Conditions
VCC/2 switch point. 30pF load. Output =1.544MHz Output =1.544MHz Output =1.544MHz Output =2.048MHz Output =2.048MHz
Delay time between SYNC and CLK1 or CLK2
T-20
T
T+20
ns
See table 12 for values of T
T 12
2
T6 = ( T 4 + T 5 )
T11 = ( T 12 + T 13 )
Specifications from AT&T Publication 62411 and ITUT Rcommendations G-823 (for 1.544MHz and 2.048MHz, respectively) T7 is guaranteed by characterization, not tested. Specifications are subject to change without notice. Rev. 1.11 5
XRT8000
AC ELECTRICAL CHARACTERISTICS (See Figure 5).
Symbol T21 T22 T23 T24 T25 T26 T27 T28 T29 T30 T31 T32 T33 Parameter CSB to SCLK Setup Time SCLK to CSB Hold Time SDI to SCLK Setup Time SCLK to SDI Hold Time SCLK Low Time SCLK High Time SCLK Period SCLK to CSB Hold Time CSB Inactive Time SCLK to SDO Valid SCLK to SDOx Delay SCLK Edge or CSB Edge to SDO HZ Rise/Fall Time SDO Output 100 40 Min. 50 20 50 50 240 240 500 50 250 200 100 Typ. Max. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns Conditions
AC Electrical Characteristics (See Figure 5)
Specifications are subject to change without notice
ABSOLUTE MAXIMUM RATINGS Supply Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7V Voltage at Any Pin . . . . . . . . . GND0.3V to Vcc +0.3V
T1 T2
Operating Temperature . . . . . . . . . . . . 40C to +85C Storage Temperature . . . . . . . . . . . . . 40C to +150C Package Dissipation . . . . . . . . . . . . . . . . . . . . 500mW
T2
FIN T3 T4 T5
CLK1 or CLK2
T9 T14
T10
T12
T7
T13
SYNC
Figure 3. Clocks Timing
Rev. 1.11 6
XRT8000
SYSTEM DESCRIPTION On power up the clock outputs of XRT8000 will be tri-stated. This means that no clocks will be seen at the outputs and lock detect output will be low. After power up the XRT8000 needs to be initialized. Therefore a serial interface is provided to load the internal registers. These registers will define the modes of operation, the output frequencies and enabling the clock outputs. Master/Forward Mode of Operation When the XRT8000 device is operating in the "Master/Forward" Mode, it will receive either an "n x 2.048 MHz" or "n x 1.544 MHz" clock signal at the FIN input (pin3); where "n" can range from 1 to 16. From this input signal, the XRT8000 device will internally divide and synthesize the following signals. At the CLK1 and/or CLK2 output pins: D k x 56 kHz D k x 64 kHz D (k x 56 kHz)/8 D (k x 64 kHz)/8 where k can range from 1 to 32. At the SYNC Output pin: D 8kHz The user selects and configures the XRT8000 device to generate these clock frequencies by writing the appropriate values into the Command Registers (CR1, CR2, CR3, CR4 and CR5), via the Microprocessor Serial Interface. Reverse Mode of Operation When the XRT8000 device is operating in the "Reverse" Mode, it will receive either a 56 kHz or 64 kHz clock signal Slave (Forward, Reverse) Mode of Operation To activate the slave modes of operations the input MSB must be tied low. In these modes an 8kHz signal must be applied to the FIN input in order to obtain output frequencies at T1 or E1 rates. The output frequencies can be selected via the serial interface in a similar fashion as described in the master forward and reverse modes. The Lock Detect Output Pin If both PLL's are enabled and in locked state then LOCKDET will be active. If one PLL loses lock then LOCKDET will be false. If only one PLL is enabled then only the active PLL will control the state of LOCKDET. at the FIN input. From this input signal, the XRT8000 device will synthesize any of the following clock signal frequencies. At the CLK1 and/or CLK2 output pins: D 1.544 MHz D 2.048 MHz D 1.544 MHz/8 = 193 kHz D 2.048 MHz/8 = 256 kHz At the SYNC output pin: D 8 kHz The user can configure the XRT8000 device to generate these clock frequencies by writing the appropriate values into the Command Registers (CR1, CR2, CR3, CR4 and CR5), via the Microprocessor Serial Interface. Note: in the REVERSE mode the contents of CR3 and CR4 has to be all one's.
Rev. 1.11 7
XRT8000
The Command Registers Between the MSB input pin and the Command Registers, the user can configure the XRT8000 device into any of the operating modes that have been described in this data sheet. The user can access these Command Registers
AD2~0 000 001 010 011 100 101 110 111 Register CR1 CR2 CR3 CR4 CR5 CR6 CR7 CR8 D4 IOC4 M4 SEL14 SEL24 SYNCEN Reserved Reserved Reserved D3 IOC3 M3 SEL13 SEL23 CLK1EN Reserved Reserved Reserved
via the Microprocessor Serial Interface. Table 1 presents the Address Location and Format for each of the Command Registers, within the XRT8000 device.
D2 IOC2 M2 SEL12 SEL22 CLK2EN Reserved Reserved Reserved D1 IOC1 M1 SEL11 SEL21 PL2/8 Reserved Reserved Reserved D0 PL1EN PL2EN SEL10 SEL10 PL1/8 Reserved Reserved Reserved
Table 1. Control Registers The next few pages describe the role/functionality of each bit-field within the Command Registers.
Rev. 1.11 8
XRT8000
CR1 Register (Power On State = "00000") D0 (PL1EN): Enable control for PLL1. If PL1EN = "1", then PLL1 is enabled. Otherwise, if PL1EN = "0", then PLL1 is disabled. D1~D4 (IOC1~IOC4): These four bit-fields function as the control bits for PLL1 and PLL2 operation modes. These bits select FORWARD, REVERSE, DATA, Kx56 or Kx64 clock rates. Multiplier "K" in Kx56 and Kx64 refers to harmonics of 56kHz or 64kHz clocks, this notation is extended to 1,544kHz and 2,048kHz frequencies in the following table (Table 2).
Note: The value of "K" for PLL1 and PLL2 are independent of each other.
Table 2 Table 2 creates the values of D1 through D4 within the CRI command register to the operating mode of the XRT8000 device.
Input Freq. [kHz] nx1544 nx1544 nx1544 nx1544 nx1544 nx1544 56 8K nx2048 nx2048 nx2048 nx2048 nx2048 nx2048 8 64 PLL1 Output [kHz] Kx56 Kx56 Kx64 Kx56 Kx64 DATA 1544 1544 Kx56 Kx56 Kx64 Kx56 Kx64 DATA 1544 2048 PLL2 Output [kHz] Kx56 Kx64 Kx64 DATA DATA DATA 1544 2048 Kx56 Kx64 Kx64 DATA DATA DATA 2048 2048
IOC4 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
IOC3 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
IOC2 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
IOC1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
Mode Forward Forward Forward Forward Forward Forward Reverse Reverse Forward Forward Forward Forward Forward Forward Reverse Reverse
Table 2. Operation Mode/Output Clock Frequency Select Options Via the D1 Through D4 Bits within the CRI Register
Note:
1 2
The values of "n" are selected via the M1 through M4 bits, within the CR2 Register (see Table 3). The values of "k" are selected via the Sel14 through SelP bits within the CR3 Register (see Table 4).
Rev. 1.11 9
XRT8000
CR2 Register (Power On State = "00000") D0 (PL2EN): Enable control for PLL2. If PL2EN = "1", then PLL2 is enabled. Otherwise, if PL2EN = "0", PLL2 is disabled. D1~D4 (M1~M4): Control bits for prescaler divider. These bits will set the divide ratio of the prescaler such that in MASTER/ FORWARD or REVERSE modes the output of this block is always at 8kHz. The settings for M4~M1 bits is based on the input frequency and the mode of operation (which is determined by the state of IOC4~IOC1 bits) is provided in Table 3.
M4 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 x x M3 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 x x M2 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 x x M1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 x x Mode Forward Forward Forward Forward Forward Forward Forward Forward Forward Forward Forward Forward Forward Forward Forward Forward Reverse Reverse Input Freq.[kHz] 1x(1544 or 2048) 2x(1544 or 2048) 3x(1544 or 2048) 4x(1544 or 2048) 5x(1544 or 2048) 6x(1544 or 2048) 7x(1544 or 2048) 8x(1544 or 2048) 9x(1544 or 2048) 10x(1544 or 2048) 11x(1544 or 2048) 12x(1544 or 2048) 13x(1544 or 2048) 14x(1544 or 2048) 15x(1544 or 2048) 16x(1544 or 2048) 56 64
Note: This table applies to MASTER (FORWARD, REVERSE) mode only
Table 3. CR2 Register
Rev. 1.11 10
XRT8000
CR3 Register (Power On State = "00000") SEL14~SEL10: These bits control two parameters: The frequency multiplier "K" for the PLL1, after selecting Kx56, Kx64 or DATA mode through register CR1 (1 < K < 32), and
1.)
The delay time between the rising edge of the sync output signal (Pin 2) and the rising edge of the CLK1 or CLI 2 output signals (See Table 6). Table 4 provides the settings for SEL14~10 bits to generate harmonic of 56kHz, 64kHz or 1.2kHz at the output of PLL1.
2.)
PLL1 Output Frequency (kHz) SEL14~SEL10 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111 K factor 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Kx56 MODE 56 112 168 224 280 336 392 448 504 560 616 672 728 784 840 896 952 1008 1064 1120 1176 1232 1288 1344 1400 1456 1512 1568 1624 1680 1736 1792 Kx64 MODE 64 128 192 256 320 384 448 512 576 640 704 768 832 896 960 1024 1088 1152 1216 1280 1344 1408 1472 1536 1600 1664 1728 1792 1856 1920 1984 2048 DATA MODE 1.2 2.4 4.8 7.2 9.6 12 14.4 16.8 19.2 21.6 24 26.4 28.8 31.2 33.6 36 38.4 40.8 43.2 43.2 43.2 43.2 43.2 43.2 43.2 43.2 43.2 43.2 43.2 43.2 43.2 43.2
Note: This table applies to forward or slave modes only
Table 4. CR3 Register
Rev. 1.11 11
XRT8000
CR4 Register (Power On State = "00000") SEL24~SEL20: These bits control the frequency multiplier "K" for the PLL2, after selecting Kx56, Kx64 or DATA mode through register CR1 (1 < K < 32). Table 5 provides the settings for SEL24~20 bits to generate harmonic of 56kHz, 64kHz or 1.2kHz at the output of PLL2.
PLL2 Output Frequency (kHz) SEL24~SEL20 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111 K factor 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Kx56 MODE 56 112 168 224 280 336 392 448 504 560 616 672 728 784 840 896 952 1008 1064 1120 1176 1232 1288 1344 1400 1456 1512 1568 1624 1680 1736 1792 Kx64 MODE 64 128 192 256 320 384 448 512 576 640 704 768 832 896 960 1024 1088 1152 1216 1280 1344 1408 1472 1536 1600 1664 1728 1792 1856 1920 1984 2048 DATA MODE 1.2 2.4 4.8 7.2 9.6 12 14.4 16.8 19.2 21.6 24 26.4 28.8 31.2 33.6 36 38.4 40.8 43.2 43.2 43.2 43.2 43.2 43.2 43.2 43.2 43.2 43.2 43.2 43.2 43.2 43.2
Note: This table applies to forward or slave forward mode only
Table 5. CR4 Register
Rev. 1.11 12
XRT8000
Table 6 presents information on the delay between the rising edge of SYNC and the CLK1 or CLKL output signals. It is important to note that this delay behaves as a function of the settings within the CR3 register.
T values (nS) SEL14~SEL10 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111 K 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Kx56 MODE 372 372 372 372 446 372 319 279 496 446 406 372 343 319 298 279 525 496 470 446 425 406 388 372 357 343 331 319 308 298 288 279 Kx64 MODE 326 326 326 326 391 326 279 244 434 301 355 326 301 279 260 244 460 434 411 391 372 355 340 326 312 301 289 279 279 260 252 244
Notes: 1 This table does not apply to the data mode or to Kx56 mode with the divide by eight enabled. 2 This table does not apply when the XRT8000 device is operating in the REVERSE Mode.
Table 6. Delay Time Between SYNC and CLK1 or CLK2
Rev. 1.11 13
XRT8000
CR5 Register (Power On State = "00000") D0 : ( PL1/8) : Select the divider by 8 for PLL1, PL1/8 = "1" CLK1 output frequency is divided by 8. PL1/8 = "0" CLK1 output frequency is as per table 4. D1 : ( PL2/8) : Select the divider by 8 for PLL2, PL2/8 = "1" CLK2 output frequency is divided by 8. PL2/8 = "0" CLK2 output frequency is as per table 5. D2 : ( CLK2EN) , PLL2: Output enable bit, CLK2EN = "1" CLK2 output is enabled. CLK2EN = "0" CLK2 output is Tri State D. D3 : ( CLK1EN) , PLL1: Output enable bit, CLK1EN = "1" CLK1 output is enabled. CLK1EN = "0" CLK1 output is Tri State D. D4 : ( SYNCEN) , 8kHz SYNC enable bit: SYNCEN = "1" SYNC output is enabled. SYNCEN = "0" SYNC output is Tri State D. CR6 to CR7 Register Register reserved for future use.
CSB
SCLK
1
2
3
4 Address
5
6
7
8
9
10
11
12 Data In
13
14
15
16
SDI
R/W
A0
A1
A2
A3
A4
A5
A6
D0
D1
D2
D3
D4
D5
D6
D7
Data Out
SDO
HiZ
D0
D1
D2
D3
D4
D5
D6
D7
HiZ
Figure 4. Serial Processor Interface Data Structure
Note: A3, A4 and A5 always Low. A6 Do not care. R/W bit = 1 for a read operation 2 for a write operation D5, D6 and D7 always Low
SERIAL INTERFACE The serial interface is a simple four wire interface that is compatible with many of the microcontrollers available in the market. This interface consists of the following signals:
Rev. 1.11 14
CSB SCLK SDI SDO
Chip Select (Active Low) Serial Clock Input Serial Data Input Serial Data Output
XRT8000
Using the Serial Interface The following instructions, for using the serial interface, are best understood by referring to the diagram in Figure 4. In order to use the serial interface the user must first provide a clock signal to the SCLK input pin. Afterwards, the user will initiates a "Read" or "Write" operation by asserting the active low Chip Select Input pin (CSB). It is important to note that the user assert CSB low coincident with the falling edge of SCLK. Once the CSB input has been asserted the type of operation and the target register address must be provided by the user. The user will provide this information to the serial interface by writing four serial bits of data to the SDI input. Note: Each of these bits will be "clocked" into the SDI input, on the rising edge of SCLK. These four bits are identified and described below. Bit 1: The R/W (Read/Write) Bit This bit will be clocked into the SDI input, on the first rising edge of SCLK (after CSB has been asserted). This bit indicates whether the current operation is a read or a write operation. A "1" in this bit will cause a "Read" operation; whereas a "0" in this bit will cause a "Write" operation. Bits 2 through 4: The three (3) bit address value (A0, A1, A2) These next three rising edges of the SCLK signal will clock in the 3-bit address value for this particular read (or write) operation. This address selects the command register within XRT8000 device that the user will either be reading data from, or writing data to. The user must supply the address bits to the SDI input pin, in ascending order with the LSB first. (A3 to A5 must be low A6 is a "don't care"). Once the "Read/Write" and Address bits have been written, the subsequent action depends upon whether the current operation is a "Read" or "Write" operation. Read Operation Once the last address bit (A2) has been clocked into the SDI input, the read operation will proceed through an idle period, lasting four SCLK periods. On the falling edge of SCLK Cycle "8" (See Figure 4) the serial output signal (SDO) becomes active. At this point the user can begin reading the data contents of the addressed command register (at Address A2, A1, A0) via the SDO pin. The SDO pin will output this five bit data word (D0 through D4) in ascending order, with the LSB first, on the rising edges of the SCLK pin. Write Operation Once the last address bit (A2) has been clocked into the SDI input, the write operation will proceed through an idle period, lasting four SCLK periods. Prior to the rising edge of SCLK Cycle #9 (See Figure 4) the user must begin to apply the eight-bit data word, that he/she wishes to write to the serial input interface onto the SDI input pin. The microprocessor serial interface will catch the value on the SDI pin on the rising edge of the SCLK. The user must apply this word (D0 through D7), serially, in ascending order with the LSB first. Simplified Interface Option The user can simplify the design of the circuitry connecting to the serial interface by tying both the SDO and SDI pins together, and reading data from and/or writing data to this "combined" signal. This simplification is possible because only one of these signals are active at any given time. The inactive signal will be tri-stated. Notes:
1. Prior to reading data from (or writing data to) the Serial Interface, the user is not required to provide a clock signal at the SCLK. However, shortly before performing any read or write operations with the Serial Interface, the user must supply the clock signal to the SCLK input pin. 2. Each Read or Write operation, with the Serial Interface, will require 16 SCLK periods, as depicted in Figure 4. 3. Upon completion of a Read or Write cycle, the user must negate CSB for at least 250ns (see timing parameter T29 in the AC Characteristics), before asserting it again for the next Read or Write operation.
Rev. 1.11 15
XRT8000
T29 CSB T21 T25 T27 T26 T28
SCLK
T22
T23 SDI
T24 W/R A0
CSB SCLK T30 SDO SDI Hz SDOD0 T31 T33 SDOD1 Hz T32 SDOD7 Hz
SDI[D7]
Figure 5. Serial Interface Timing
Rev. 1.11 16
XRT8000
CONFIGURATION DIAGRAMS The following six figures depict all of the configuration possibilities for the XRT8000. The table in the left (FIN) lists different possibilities for reference clock input, while the table in the right lists all the possibilities for two output clocks.
k
Output Frequencies (kHz) (k x 56) (k x 56)/8 56 112 168 224 280 336 392 448 504 560 616 672 728 784 840 896 952 1,008 1,064 1,120 1,176 1,232 1,288 1,344 1,400 1,456 1,512 1,568 1,624 1,680 1,736 1,792 7 14 21 28 35 42 49 56 63 70 77 84 91 98 105 112 119 126 133 140 147 154 161 168 175 182 189 196 203 210 217 224 (k x 64) 64 128 192 256 320 384 448 512 576 640 704 768 832 896 960 1,024 1,088 1,152 1,216 1,280 1,344 1,408 1,472 1,536 1,600 1,664 1,728 1,792 1,856 1,920 1,984 2,048 (k x 64)/8 8 16 24 32 40 48 56 64 72 80 88 96 104 112 120 128 136 144 152 160 168 176 184 192 200 208 216 224 232 240 248 256
n x T1 or n x E1 (1<=n<=16) Reference Freq. (kHz) n x T1 1,544 3,088 4,632 6,176 7,720 9,264 10,808 12,352 13,896 15,440 16,984 18,528 20,072 21,616 23,160 24,704 n x E1 2,048 4,096 6,144 8,192 10,240 12,288 14,336 16,384 18,432 20,480 22,528 24,576 26,624 28,672 30,720 32,768
XRT8000
FIN CLK1 k x DS0 (1<=k<=32) CLK2 SYNC
8 kHz
n 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
Figure 6. Master Forward Mode
Rev. 1.11 17
XRT8000
XRT8000
n x T1 n x E1 (1<=n<=16) FIN Output Frequencies (Hz) k 0.5 1 2 3 4 5 CLK1 6 7 k x 2.4 kHz (1<=k<=18) 8 9 10 11 12 13 14 SYNC 8 kHz 15 16 17 18 (k x 2400) (k x 2400)/8 1,200 2,400 4,800 7,200 9,600 12,000 14,400 16,800 19,200 21,600 24,000 26,400 28,800 31,200 33,600 36,000 38,400 40,800 43,200 150 300 600 900 1,200 1,500 1,800 2,100 2,400 2,700 3,000 3,300 3,600 3,900 4,200 4,500 4,800 5,100 5,400
n 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Reference n x T1 1,544 3,088 4,632 6,176 7,720 9,264 10,808 12,352 13,896 15,440 16,984 18,528 20,072 21,616 23,160 24,704
Freq.n (kHz) x T1 or n x E1 2,048 4,096 6,144 8,192 10,240 12,288 14,336 16,384 18,432 20,480 22,528 24,576 26,624 28,672 30,720 32,768 CLK2
Figure 7. Master Forward Mode (Cont'd)
Rev. 1.11 18
XRT8000
64 kHz or 56 kHz
XRT8000
FIN Output CLK1 T1, T1/8 or E1, E1/8 CLK2 SYNC 8 kHz kHz 1544 2048 Freq. kHz 193 256
Figure 8. Master Reverse Mode
k 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Output Frequencies (kHz) (k x 56)/8 (k x 64) (k x 64)/8 7 64 8 14 128 16 21 192 24 28 256 32 35 320 40 42 384 48 49 448 56 56 512 64 63 576 72 70 640 80 77 704 88 84 768 96 91 832 104 98 896 112 105 960 120 112 1,024 128 119 1,088 136 126 1,152 144 133 1,216 152 140 1,280 160 147 1,344 168 154 1,408 176 161 1,472 184 168 1,536 192 175 1,600 200 182 1,664 208 189 1,728 216 196 1,792 224 203 1,856 232 210 1,920 240 217 1,984 248 224 2,048 256
XRT8000
8 kHz FIN
CLK1 k x DS0 (1<=k<=32) CLK2
SYNC
8 kHz
(k x 56)/8 56 112 168 224 280 336 392 448 504 560 616 672 728 784 840 896 952 1,008 1,064 1,120 1,176 1,232 1,288 1,344 1,400 1,456 1,512 1,568 1,624 1,680 1,736 1,792
Figure 9. Slave Forward Mode
Rev. 1.11 19
XRT8000
k 0.50 1 2 3 Output Frequencies (Hz) (k x 2400) 1,200 2,400 4,800 7,200 9,600 12,000 14,400 16,800 19,200 21,600 24,000 26,400 28,800 31,200 33,600 36,000 38,400 40,800 43,200 (k x 2400)/8 150 300 600 900 1,200 1,500 1,800 2,100 2,400 2,700 3,000 3,300 3,600 3,900 4,200 4,500 4,800 5,100 5,400
XRT8000
8 kHz FIN
4 5 6 7
CLK1 k x 2.4 kHz (1<=k<=18) CLK2
8 9 10 11 12 13 8 kHz 14 15 16 17 18
SYNC
Figure 10. Slave Forward Mode (Cont'd)
Rev. 1.11 20
XRT8000
XRT8000
8 kHz FIN CLK1 T1, T1/8 or E1, E1/8 CLK2 SYNC 8 kHz Output kHz 1544 2048 Freq. kHz 193 256
Figure 11. Slave Reverse Mode (Cont'd)
Board Layout Considerations The CLK1 and CLK 2 outputs are surrounded with supply pins (GND(514),Vcc(712). It is recommended to decouple these supplies with a 0.1uF very close to the pins. The positive supply (7,12,15) and ground pins (4,5,14) can all be connected to the Digital Supply and Ground. The internal VCO has its proper supply's pins (GND 9, Vcc 10) these supply pins have to be decoupled by a 0.1uF capacitor and should be connected to an Analog Supply if possible. If there is no Analog Supply, then connect these pins as close as possible to the supply source. If the layout is done with separate layers for the supplies, cut an island under the XTT8000 such that no current flows under the circuit. It has been observed that coupling can occur because heavy digital currents are flowing under the locations of the XRT8000.
Rev. 1.11 21
XRT8000
18 LEAD PLASTIC DUALINLINE (300 MIL PDIP)
Rev. 1.00
18 1 D A L B
10 9
E1 E
Seating Plane
A2
A1 e B1
a
eA eB
C
INCHES SYMBOL A A1 A2 B B1 C D E E1 e eA eB L MIN 0.145 0.015 0.115 0.014 0.030 0.008 0.845 0.300 0.240 MAX 0.210 0.070 0.195 0.024 0.070 0.014 0.925 0.325 0.280
MILLIMETERS MIN 3.68 0.38 2.92 0.36 0.76 0.20 21.46 7.62 6.10 MAX 5.33 1.78 4.95 0.56 1.78 0.38 23.50 8.26 7.11
0.100 BSC 0.300 BSC 0.310 0.115 0 0.430 0.160 15
2.54 BSC 7.62 BSC 7.87 2.92 0 10.92 4.06 15
a
Note: The control dimension is the inch column
Rev. 1.11 22
XRT8000
18 LEAD SMALL OUTLINE (300 MIL JEDEC SOIC)
Rev. 1.00
D
18
10
E
1 9
H
C Seating Plane e B A1 L A
a
INCHES SYMBOL A A1 B C D E e H L MIN 0.093 0.004 0.013 0.009 0.447 0.291 0.394 0.016 0 MAX 0.104 0.012 0.020 0.013 0.463 0.299 0.419 0.050 8
MILLIMETERS MIN 2.35 0.10 0.33 0.23 11.35 7.40 10.00 0.40 0 MAX 2.65 0.30 0.51 0.32 11.75 7.60 10.65 1.27 8
0.050 BSC
1.27 BSC
a
Note: The control dimension is the millimeter column
Rev. 1.11 23
XRT8000
NOTICE EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained herein are only for illustration purposes and may vary depending upon a user's specific application. While the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circumstances. Copyright 1999--2006 EXAR Corporation Datasheet September 2006 Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.
Rev. 1.11 24

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